Substrate-blased silicon diode for electrostatic discharge protection and fabrication method

ABSTRACT

An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention pertains in general to a semiconductor device, and, more particularly, to a substrate-biased silicon diode and a method for making the same.

[0003] 2. Description of the Related Art

[0004] A semiconductor integrated circuit (IC) is generally susceptible an electrostatic discharge (ESD) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is provided to the IC. The high current may be built-up from a variety of sources, such as the human body. Many schemes have been implemented to protect an IC from an ESD event. A common protection scheme is using a parasitic transistor associated with an n-type metal-oxide semiconductor (MOS) with the source coupled to ground and the drain connected to the pin to be protected from an ESD event.

[0005] Diodes or diode-coupled transistors have been used for ESD protection in radio-frequency (RF) applications. In a RF IC, an on-chip ESD circuit should ideally provide robust ESD protection, while exhibiting minimum parasitic input capacitance and low voltage-dependency. In deep-submicron complementary metal-oxide semiconductor (CMOS) process technology with shallow-trench isolations (STIs), a diode has been used for ESD protection and is generally formed contiguous with either an N⁺or P⁺diffusion region in a semiconductor substrate. FIG. 1A shows a cross-sectional view of a known diode ESD protection structure formed in an IC. Referring to FIG. 1A, a P⁺diffusion region is bound by STIs on either side, and therefore the diode formed by the STI is also known as an STI-bound diode. The STI-bound diode exhibits a bottom capacitance, C_(bottom). However, an STI-bound diode has been found to have significant leakage current due to an interference between a silicide layer (not shown) of the P⁺diffusion region and the STIs around the P⁺region.

[0006]FIG. 1B shows a cross-sectional view of another known diode ESD protection structure, known as a polysilicon-bound diode, introduced to address the leakage current problem with an STI-bound diode. The P⁺diffusion region in a polysilicon-bound diode is now defined by a polysilicon gate, and therefore the leakage current from the edges of STIs is eliminated. However, the total parasitic capacitance of the polysilicon-bound diode is larger than that of the STI-bound diode because of the addition of the sidewall junction capacitance of the P⁺diffusion region.

[0007]FIG. 2 is a circuit diagram showing a known ESD protection scheme using dual diodes. Referring to FIG. 2, the combination of the dual-diode structures and V_(DD)-to-V_(ss) ESD clamp circuit provides a path for an ESD current 2 to discharge, instead of through the internal circuits. When ESD current 2 is provided to signal a pad PAD1, and with a signal pad PAD2 relatively grounded, ESD current 2 is conducted to V_(DD) through Dp1. ESD current 2 is discharged to V_(ss) through the V_(DD)-to-V_(SS) ESD clamp circuit and flows out of the IC from Dn2 to PAD2. Diode Dp1 has a capacitance of Cp1 and diode Dn1 has a capacitance of Cn1. The total input capacitance C_(m) of the circuit shown in FIG. 2 primarily comes from the parasitic junction capacitance of diodes, and is calculated as follows:

C_(in)=Cp1+Cn1

[0008] wherein Cp1 and Cn1 are parasitic junction capacitances of diodes Dp1 and Dn1, respectively.

[0009]FIG. 3 is plot showing the relationship between a pad voltage and parasitic input capacitance of the circuit shown in FIG. 2. Referring to FIG. 3, when the voltage on the pad increases, the parasitic junction capacitance of Dp1 increases and the parasitic junction capacitance of Dn1 decreases. Therefore, the total input parasitic capacitance C_(in) is nearly constant. This characteristic is important in RF applications. However, the total parasitic capacitance of a polysilicon-bound diode, as compared to an STI-bound diode, is increased because of the addition of a sidewall capacitance, C_(sidewall), as shown in FIG. 1B.

SUMMARY OF THE INVENTION

[0010] Accordingly, the present invention is directed to a substrate-biased silicon diode and a method for making the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

[0011] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.

[0012] To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer disposed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions, wherein the p-type portion overlaps the first isolation structure and the n-type portion overlaps the second isolation structure.

[0013] Also in accordance with the present invention, there is provided an integrated circuit device receiving signals from a signal pad that includes at least one substrate-biased silicon diode responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals.

[0014] In one aspect of the invention, each of the at least one substrate-biased silicon diode includes a p-type silicon portion, an n-type silicon portion and a center silicon portion disposed between and contiguous with the p-type and n-type silicon portions.

[0015] In another aspect of the invention, there additionally includes a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one substrate-biased silicon diode.

[0016] Further in accordance with the present invention, there is provided an integrated circuit device receiving signals from a signal pad that includes a first plurality of serially coupled substrate-biased silicon diodes responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals, each of the first plurality of substrate-biased silicon diodes including a p-portion and an n-portion, a second plurality of serially coupled substrate-biased silicon diodes responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals, each of the second plurality of substrate-biased silicon diodes including a p-portion and an n-portion, and a detection circuit for detecting signals from the signal pad and providing a bias voltage to the first and second plurality of substrate-biased silicon diodes, wherein the signal pad is coupled to the p-portion of one of the first plurality of substrate-biased silicon diodes and the n-portion of one of the second plurality of the substrate-biased silicon diodes

[0017] Additionally in accordance with the present invention, there is provided an integrated circuit device that comprises a semiconductor substrate, an insulator layer disposed over the semiconductor substrate, a silicon layer disposed over the insulator layer, which includes a first isolation structure formed inside the silicon layer, and a second isolation structure formed inside the silicon layer and spaced apart from the first isolation structure, a dielectric layer disposed over the silicon layer, and a layer of silicon, disposed over the dielectric layer, which includes a p-type portion, an n-type portion and a center portion disposed between and contiguous with the p-type and n-type portions.

[0018] Further in accordance with the present invention, there is provided a silicon-on-insulator circuit device receiving signals from a signal pad that includes at least one base-biased silicon diode, responsive to the signals from the signal pad, for providing electrostatic discharge protection.

[0019] In one aspect of the invention, the silicon-on-insulator is biased to control the at least one base-biased silicon diode.

[0020] Additionally in accordance with the present invention, there is provided a method for protecting a silicon-on-insulator device from electrostatic discharge that includes the steps of providing a signal to the device through a silicon-on-insulator circuit, providing a base-biased silicon diode in the silicon-on-insulator circuit, and protecting the device from electrostatic discharge produced with the base-biased silicon diode.

[0021] Also in accordance with the present invention, there is provided a method for protecting a complementary metal-oxide semiconductor device from electrostatic discharge that includes the steps of providing a signal to the device through a complementary metal-oxide semiconductor circuit, providing a substrate-biased silicon diode in the complementary metal-oxide semiconductor circuit, and protecting the device from electrostatic discharge produced from the signal with the substrate-biased silicon diode.

[0022] Moreover in accordance with the present invention, there is provided a method for forming a silicon diode that includes the steps of A method for forming a silicon diode, comprising the steps of forming a first silicon layer, forming a first isolation structure and a second isolation structure inside the first silicon layer, the first isolation structure being spaced apart from the second isolation structure, forming a dielectric layer over the silicon layer, forming a second silicon layer over the dielectric layer, forming dielectric spacers contiguous with the second silicon layer, implanting a first impurity having a first concentration into a first portion and a second portion of the second silicon layer, the first portion being contiguous with the second portion and the second portion overlapping a region of the first silicon layer between the first isolation structure and the second isolation structure, implanting a first impurity having a second concentration into the first portion of the second silicon layer, wherein the second concentration is greater than the first concentration, and implanting a second impurity into a third portion of the second silicon layer, wherein the third portion is contiguous with the second portion.

[0023] In one aspect of the invention, the steps of implanting a first impurity having a first concentration and implanting a first impurity having a second concentration create a diffused region adjacent one of first and second field isolation structures.

[0024] Also in accordance with the present invention, there is provided a method for forming a base-biased silicon diode that includes the steps of forming a first and second isolation structures inside a silicon layer, defining a base region inside the silicon layer, the base region being disposed between and contiguous with the first and second isolation structures, forming a dielectric layer over the well region, forming a layer of silicon over the dielectric layer, implanting a first impurity having a first concentration into a first portion and a second portion of the silicon layer, wherein the first portion is contiguous with the second portion and the second portion overlapping a region of the silicon layer between the first isolation structure and the second isolation structure, implanting a first impurity having a second concentration into the first portion and second portion of the silicon layer, wherein the second concentration is greater than the first concentration, and implanting a second impurity into a third portion of the silicon layer, wherein the third portion is contiguous with the second portion and overlaps the second isolation structure.

[0025] Further in accordance with the present invention, there is provided a method for forming a substrate-biased silicon diode that includes the steps of forming a first isolation structure and a second isolation structure spaced apart from the first isolation structure inside a silicon layer, forming a dielectric layer over the silicon layer, forming a layer of silicon having two ends over the dielectric layer, forming dielectric spacers contiguous with the two ends of the silicon layer, implanting a first impurity having a first concentration into a first portion and a second portion of the silicon layer, wherein the first portion is contiguous with the second portion and overlaps the first isolation structure, implanting a second impurity into a third portion of the silicon layer, wherein the third portion is contiguous with the second portion and overlaps the second isolation structure, and implanting a first impurity having a second concentration into the first portion of the silicon layer, wherein the second concentration is greater than the first concentration.

[0026] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the objects, advantages, and principles of the invention.

[0028] In the drawing:

[0029]FIG. 1A shows a cross-sectional view of a known diode structure formed in an integrated circuit;

[0030]FIG. 1B shows a cross-sectional view of another known diode structure formed in an integrated circuit;

[0031]FIG. 2 is a circuit diagram of a known ESD protection circuit;

[0032]FIG. 3 is plot showing the relationship between a pad voltage and parasitic input capacitance of the circuit shown in FIG. 2;

[0033]FIG. 4 shows a cross-sectional view of a silicon diode in accordance with one embodiment of the present invention;

[0034]FIG. 5 shows a cross-sectional view of a silicon diode in accordance with another embodiment of the present invention;

[0035]FIG. 6 shows a cross-sectional view of a base-biased silicon diode in accordance with one embodiment of the present invention;

[0036]FIG. 7 is a layout diagram of the base-biased silicon diode of FIG. 5;

[0037] FIGS. 8A-8H are cross-sectional views of the steps in a method of forming a substrate-biased silicon diode with an n-type center region;

[0038] FIGS. 9A-9H are cross-sectional views of the steps in a method of forming a substrate-biased silicon diode with a p-type center region;

[0039]FIG. 10 shows the circuit symbol for the substrate-biased silicon diode of the present invention relative to the cross-sectional view of the diode;

[0040]FIG. 11 is a circuit diagram of an ESD protection circuit with dual substrate-biased silicon diodes of the present invention;

[0041]FIG. 12A is plot showing the relationship between a pad voltage and individual parasitic input capacitance of the dual substrate-biased silicon diodes of FIG. 10;

[0042]FIG. 12B is plot showing the relationship between a pad voltage and total parasitic input capacitance of the dual substrate-biased silicon diodes of FIG. 10;

[0043]FIG. 13A is a circuit diagram of one embodiment of an ESD protection circuit using substrate-biased silicon diodes of the present invention;

[0044]FIG. 13B is a circuit diagram of one embodiment of an ESD protection circuit using stacked substrate-biased silicon diodes of the present invention;

[0045]FIG. 13C is a circuit diagram of another embodiment of an ESD protection circuit using stacked substrate-biased silicon diodes of the present invention; and

[0046]FIG. 14 is a circuit diagram of one embodiment of an ESD protection circuit with biased dual substrate-biased silicon diodes of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] In accordance with the present invention, there is provided a substrate-biased polysilicon diode (SBPD) for ESD protection. The SBPD of the present invention is biased from the substrate for an improved turn-on speed of the SBPD and reduced leakage current. Unlike conventional diodes, an SBPD does not have a bottom junction capacitance and therefore exhibits a relatively smaller junction capacitance. In addition, because an SBPD is disposed over shallow trench isolations (STIs) in a silicon substrate, the silicon area used by the SBPD is reduced, which reduces cost. The SBPD of the present invention additionally provides a substrate-biased function, and therefore provides more flexibility in RF IC applications.

[0048]FIG. 4 shows a cross-sectional view of an SBPD in accordance with one embodiment of the present invention. Referring to FIG. 4, an integrated circuit 10 includes a semiconductor substrate 12 and a well region 14 formed inside semiconductor substrate 12. Two isolation structures 16 are formed inside well region 14 and are spaced apart from one another. Isolation structures may be conventional STIs used for device isolation. Integrated circuit 10 also includes a diffused region 20 adjacent one of STIs 16. Diffused region 20 is doped with the same type of impurity as well region 14. Integrated circuit 10 may also include another diffused region 18 adjacent one of STIs 16. In one embodiment of the invention, semiconductor substrate 12 is a p-type substrate, well region 14 is an n-well, and diffused region 20 is an n-type diffused region. The optional diffused region 18 is a p-type diffused region.

[0049] A dielectric layer 22 is formed over the well region 14, overlapping STIs 16 and a portion of well region 14A disposed between STIs 16. Dielectric layer 22 may be an oxide layer. A layer of silicon 32, subsequently becomes an SBPD, is disposed over dielectric layer 22. Silicon layer 32 includes a p-type portion 24, an n-type portion 26, and a center portion 28 disposed between p-type portion 24 and n-type portion 26. P-type portion 24 overlaps one of STIs 16 and n-type portion 26 overlaps the other one of STIs 16. Center portion 28 overlaps well region portion 14A. In one embodiment, center portion 28 of silicon layer 32 is doped with an n-type impurity having a doped concentration lower than that of n-type portion 26. In another embodiment, center portion 28 of silicon layer 32 is doped with a p-type impurity having a doped concentration lower than that of p-type portion 24. In addition, in an embodiment in which diffused region 20 is an n-type diffused region, diffused region 20 is adjacent one of STIs 16 and n-type portion 26 of silicon layer 32. A plurality of contacts 30 are formed inside diffused region 20, p-type portion 24 and n-type portion 26 of silicon layer 32.

[0050] In operation, SBPD 32 responds to ESD pulses to provide electrostatic discharge protection. Furthermore, well region 14 can be biased to control SBPD 32. In one embodiment, diffused region 20 is biased to cause well region 14 to be biased to control SBPD 32 for providing electrostatic discharge protection.

[0051]FIG. 5 shows a cross-sectional view of a silicon diode in accordance with another embodiment of the present invention. Referring to FIG. 5, an integrated circuit 200 includes a semiconductor substrate 202 and a dielectric layer 204 formed over semiconductor substrate 202. Dielectric layer 204 may comprise a conventional STI. Integrated circuit 200 also includes a layer of silicon 206, subsequently becomes a silicon diode, is disposed over dielectric layer 204. Silicon layer 206 includes a p-type portion 208, an n-type portion 210, and a center portion 212 disposed between p-type portion 208 and n-type portion 210. In one embodiment, center portion 212 is undoped and may be fabricated in a salicide CMOS process. The silicon diode thus formed has no junction in semiconductor substrate 202, eliminating substrate noise coupling.

[0052]FIG. 6 shows a cross-sectional view of a base-biased silicon diode in accordance with another embodiment of the present invention. Referring to FIG. 6, the SBPD of the present invention is implemented in a silicon-on-insulator (SOI) CMOS integrated circuit 34. An insulator 38 is disposed over a semiconductor substrate 36. A silicon layer 40 is disposed over insulator layer 38 and includes an isolation structure 42 formed inside silicon layer 40 and an isolation structure 44 formed inside silicon layer 40 and spaced apart from isolation structure 42. Silicon layer 40 also includes a base portion 46 disposed between and contiguous with isolation structures 42 and 44. In one embodiment of the present invention, substrate 36 is a p-type substrate, and isolation structures 42 and 44 are STIs.

[0053] A dielectric layer (not shown) is disposed over silicon layer 40, and a layer of polysilicon 52 is disposed over the dielectric layer. Polysilicon layer 52 may also be a silicon layer. Polysilicon layer 52 includes a p-type portion 50, an n-type portion 48 and a center portion (not shown) disposed between and contiguous with the p-type and n-type portions 48 and 50. In addition, p-type portion 50 overlaps isolation structure 44 and n-type portion 48 overlaps isolation structure 42. The center portion of polysilicon layer 52 overlaps base portion 46. Integrated circuit 34 may additional comprise a diffused region (not shown) inside silicon layer 40 adjacent one of isolation structures 42 and 44. Integrated circuit 34 also comprises a plurality of contacts 54.

[0054] In operation, insulator layer 38 isolates devices in SOI integrated circuit 34. Thus, silicon diode 52 of the present invention is adapted to be base-biased. The bias supply for based-biased silicon diode 52 may be located on one or both sides of based-biased silicon diode 52 in the form of diffused region adjacent one of isolation structure 42 and 44. Base portion 46 of silicon layer 40 may also be biased to control based-biased silicon diode 52 to provide electrostatic discharge protection. Therefore, this embodiment of the present invention appropriately named a base-biased silicon diode. FIG. 7 is a layout diagram of base-biased silicon diode 52 as shown in FIG. 6 along the A-A′ direction.

[0055] FIGS. 8A-8H are cross-sectional views of the steps in a method of forming a substrate-biased silicon diode of the present invention. Referring to FIG. 8A, a semiconductor substrate 12 is prepared and defined. In one embodiment, semiconductor substrate 12 is a p-type substrate. FIG. 8B shows the formation of STIs 16 inside semiconductor substrate 12. In general, STIs are formed by providing a mask over a substrate. After the mask is patterned and defined, the semiconductor substrate is etched to form shallow trenches spaced apart from one another. A dielectric material, such as silicon dioxide, silicon nitride or silicon oxynitride, is deposited to fill the trenches. The mask is then removed.

[0056]FIG. 8C shows an implantation of impurities to form a well region. Referring to FIG. 8C, after a photoresist 56 is patterned and defined, substrate 12 is doped with an impurity to form well 14. In one embodiment, substrate 12 is doped with an n-type impurity to form an n-well. After implantation, photoresist 56 is removed.

[0057]FIG. 8D shows the beginning of the formation of a silicon diode. Referring to FIG. 8D, a thin oxide layer 58 is grown over the surface of well region 14. A layer of silicon 32 is then deposited over oxide layer 58. A photoresist (not shown) is used to pattern and define silicon layer 32 during an etching process to form the structure shown in FIG. 8D. Conventional steps follow to form spacers 62 contiguous with silicon layer 32. Spacers 62 may be oxide spacers or nitride spacers.

[0058] Referring to FIG. 8E, a photoresist 64 is deposited over silicon layer 32, spacers 62, well 14, and substrate 12, and then patterned and defined to expose a first portion 26 of silicon layer 32, a portion of silicon layer 32 that would later become center portion 28, and a portion of well 14. A lightly-doped drain (LDD) of an impurity is implanted into first portion 26, center portion 28, and the exposed portion of well 14. The implanted impurity forms a diffused region 20 in well region 14. Therefore, first portion 26 contains the same type of impurity as center portion 28 and diffused region 20. In one embodiment, an LDD of an n-type impurity is implanted into first portion 26, center portion 28, and diffused portion 20.

[0059] Referring to FIG. 8F, a photoresist 65 is deposited over silicon layer 32, spacers 62, well 14, and substrate 12, and then patterned and defined to expose first portion 26 and diffused region 20. A high concentration of the same type of impurity implanted in FIG. 8E is implanted into first portion 26 and diffused region 20. The high concentration implant of FIG. 8F provides a higher concentration than the LDD implant of FIG. 8E. Diffused region 20 is implanted with the same type of impurity as first portion 26. After the high concentration implantation, diffused region 20 diffuses further into well 14, and first portion 26 now contains a higher concentration of impurity. Therefore, center portion 28 contains a lower concentration of impurities than first portion 26. Photoresist 65 is then removed. In one embodiment, a high concentration of an n-type impurity is implanted, and first portion 26 becomes the n-portion of an SBPD.

[0060] Referring to FIG. 8G, a photoresist 66 is deposited over silicon layer 32, spacers 62, well 14, and substrate 12. Photoresist 66 is patterned and defined to expose a second portion 24 of silicon layer 32. An impurity of a different type than the LDD and high concentration implants of FIGS. 8E and 8F is implanted into second portion 24. Second portion 24 is heavily doped with the different impurity. In one embodiment, second portion 24 is heavily doped with a p-type impurity and become the p-portion of an SBPD. Photoresist 66 is then removed. Referring to FIG. 8H, conventional semiconductor processing follows to form a plurality of contacts 30.

[0061] Similar to the method of forming an SBPD shown in FIGS. 8A-8H above, FIGS. 9A-9H are cross-sectional views of the steps in a method of forming a substrate-biased silicon diode with a p-type center region. Referring to FIG. 9A, a p-type semiconductor substrate 112 is prepared and defined. FIG. 9B shows the formation of STIs 116 inside semiconductor substrate 112. STIs 116 may be formed using the process steps described above. FIG. 9C shows an n-well implantation to form an n-well region. Referring to FIG. 9C, after a photoresisit 156 is patterned and defined, substrate 112 is doped with an n-type impurity to form n-well 114. In addition, STIs 116 are now disposed inside n-well 114. After implantation, photoresist 156 is removed.

[0062] Referring to FIG. 9D, a thin oxide layer 158 is grown over the surface of n-well 114. A layer of silicon 132 is then deposited over oxide layer 158. A photoresist (not shown) is used to pattern and define polysilicon layer 132 during etching to form the structure shown in FIG. 9D. Conventional steps follow to form spacers 162 contiguous with polysilicon layer 132. Spacers 162 may be oxide spacers or nitride spacers.

[0063] Referring to FIG. 9E, after a photoresist 168 is deposited over polysilicon layer 132, spacers 162, n-well 114, and substrate 112, photoresist 168 is patterned and defined to expose a second portion 124 of polysilicon layer 132. A p-type lightly-doped drain (LDD) is implanted into second portion 124. Photoresist 168 is removed after the implantation step.

[0064] Referring to FIG. 9F, a photoresist 170 is deposited over polysilicon layer 132, spacers 162, n-well 114, and substrate 112. Photoresist 170 is patterned and defined to expose a first portion of polysilicon layer 126, a portion of polysilicon layer 132 that would later become a center portion 128, and a portion of n-well 114. A high-concentration n-type impurity is implanted into first portion 126, center portion 128, and the portion of n-well 114. Implanted portion of n-well 114 becomes an n-type diffused region 120. Photoresist 170 is then removed.

[0065] Referring to FIG. 9G, a photoresist 172 is laid down and patterned. Using photoresist 172 as a mask, a high concentration of a p-type impurity is implanted into second portion 124. The implantation concentration of the step shown in FIG. 9G is larger than that of the LDD implantation step shown in FIG. 9E. The p-portion 124 of an SBPD is formed and contains a higher impurity concentration than center region 128 of the SBPD. Photoresist 172 is then removed. Referring to FIG. 9H, conventional semiconductor processing follows to form a plurality of contacts 130.

[0066] For a silicon diode of the present invention manufactured using an SOI technology, a modification of the manufacturing processes described above will be required. However, the modification will be limited to the few steps at the beginning of the manufacturing process unrelated to the manufacturing steps for the formation of the silicon diode. With the exception of the steps related to the creating of a well region, the manufacturing steps described above follow to manufacture a base-biased silicon diode of the present invention as described above.

[0067]FIG. 10 is a circuit symbol for an SBPD of the present invention relative to the cross-sectional view of the diode. FIG. 11 is a circuit diagram of an ESD protection circuit with two dual-SBPDs. The first dual SBPDs include SBPD1 and SBPD2, and second dual SBPDs include SBPD3 and SBPD4. Referring to FIG. 11, dual silicon diodes SBPD1 and SBPD2 are used in a forward-biased condition to discharge an ESD current so that the ESD current does not damage the internal circuits. When an ESD current 4 is applied to Pad1, and with Pad2 grounded relative to Pad1, an ESD current 4 is conducted to VDD through silicon diode SBPD1. ESD current 4 is then discharged to the VSS line through a VDD-to-VSS ESD clamp circuit 6 and flows out of the IC through SBPD4.

[0068] Therefore, the present invention also includes a method for protecting a CMOS semiconductor device from electrostatic discharge. The method provides a signal to the semiconductor device through a CMOS semiconductor circuit that includes at least one substrate-biased silicon diode to protect the semiconductor device from electrostatic discharge. Similarly, the present invention also includes a method for protecting a silicon-on-insulator semiconductor device from electrostatic discharge. The method provides a signal to the device through a silicon-on-insulator circuit that includes at least one base-biased silicon diode to protect the semiconductor device from electrostatic discharge.

[0069]FIG. 12A is plot showing the relationship between a pad voltage and individual parasitic input capacitance of the dual substrate-biased silicon diodes of FIG. 11. When the n-well region of an SBPD is biased to ground, the parasitic capacitance of the SBPD is approximately half of the polysilicon-bound diode of FIG. 1B because, unlike a polysilicon-bound diode, an SBPD does not have a bottom junction capacitance, C_(bottom). As shown in FIG. 12A, the capacitance variation of an SBPD relative to pad voltages is similar to that of a polysilicon-bound diode as shown in FIG. 3. Therefore, the total input capacitance C_(in) of the dual SBPDs of FIG. 11 is also approximately half of the dual polysilicon-bound diodes. This relationship is shown in FIG. 12B.

[0070] The input parasitic capacitance of SBPDs may be further reduced by connecting a plurality of SBPDs in series because capacitances connected in series lower the total capacitance. FIG. 13A is a circuit diagram of one embodiment of an ESD protection circuit using dual SBPDs. Assuming each of the SBPDs has the same capacitance C, the total capacitance for FIG. 13A is 2C. FIG. 13B is a circuit diagram of one embodiment of an ESD protection circuit using two dual-SBPDs. The total capacitance for FIG. 13B is C. FIG. 13C is a circuit diagram of another embodiment of an ESD protection circuit using dual SBPD strings. The total capacitance for FIG. 13C is 2C/n, wherein n represents the number of SBPDs.

[0071]FIG. 14 is a circuit diagram of one embodiment of an ESD protection circuit with biased dual SBPDs of the present invention. Referring to FIG. 14, an integrated circuit device 74 receives signals from a signal pad 76. Device 74 includes a pair of SBPDs 78 and 80, responsive to the signals from signal pad 76 for providing electrostatic discharge protection from the signals. Each of SBPDs 78 and 80 includes a p-portion and an n-portion (not numbered) and signal pad 76 is coupled to the p-portion of one of the pair of SBPDs and the n-portion of the other one of the pair of SBPDs. In one embodiment of the invention as shown in FIG. 11, device 74 additionally comprises a second pair of SBPDs, SBPD3 and SBPD4, coupled to clamp circuit 6. In another embodiment as shown in FIG. 13C, each of the pair of SBPDs 78 and 80 of FIG. 14 includes a plurality of serially coupled SBPDs.

[0072] Referring again to FIG. 14, device 74 further comprises a detection circuit 86 for detecting signals from signal pad 76 and providing a bias voltage to SBPDs 78 and 80. In one embodiment, an integrated circuit that receives electrostatic charges from a signal pad comprises a plurality of serially coupled SBPDs responsive to the electrostatic pulses from the signal pad for providing electrostatic discharge protection from the signals. Detection circuit 78 comprises a resistor-capacitor (R-C) circuit having a delay constant longer than the duration of the electrostatic pulses. The resistor-capacitor circuit is coupled in parallel with a transistor network. The transistor network comprises a first transistor 84, and a second transistor 82, and each of the transistors includes a gate, source and drain. The gate of first transistor 84 is coupled to the gate of second transistor 82 and the resistor-capacitor circuit. In addition, the drain of first transistor 84 and the drain of the second transistor 82 are coupled to a substrate of SBPDs 78 and 80. The source of first transistor 84 is coupled to a VDD signal and the source of second transistor 82 is coupled to a VSS signal. In operation, the drain of first transistor 84 and the drain of the second transistor 82 are coupled to the substrate of SBPDs 78 and 80 to provide a bias voltage.

[0073] It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed process without departing from the scope or spirit of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. 

What is claimed is:
 1. An integrated circuit device, comprising a semiconductor substrate; a well region formed inside the semiconductor substrate; a first isolation structure formed inside the well region; a second isolation structure formed inside the well region and spaced apart from the first isolation structure; a dielectric layer disposed over the well region; and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions, wherein the p-type portion overlaps the first isolation structure and the n-type portion overlaps the second isolation structure.
 2. The integrated circuit device as claimed in claim 1, wherein the center portion of the layer of silicon is doped with an n-type impurity having a doped concentration lower than that of the n-type portion.
 3. The integrated circuit device as claimed in claim 1, wherein the center portion of the layer of silicon is doped with a p-type impurity having a doped concentration lower than that of the p-type portion.
 4. The integrated circuit device as claimed in claim 1, wherein the center portion of the layer of silicon is undoped.
 5. The integrated circuit device as claimed in claim 1, wherein the center portion overlaps a portion of the well region between the first and second isolation structures.
 6. The integrated circuit device as claimed in claim 1, further comprising a diffused region formed inside the well region adjacent one of the first and second isolation structures.
 7. The integrated circuit device as claimed in claim 6, wherein the diffused region is biased to cause the well region to be biased to control the silicon layer for providing electrostatic discharge protection.
 8. An integrated circuit device receiving signals from a signal pad, comprising at least one substrate-biased silicon diode responsive to the signals from the signal pad for providing electrostatic discharge protection.
 9. The integrated circuit device claimed in claim 8, wherein the at least one substrate-biased silicon diode includes one or more serially coupled substrate-biased silicon diodes.
 10. The integrated circuit device as claimed in claim 8, wherein the at least one substrate-biased silicon diode includes a p-type polysilicon portion, an n-type polysilicon portion and a center polysilicon portion disposed between and contiguous with the p-type and n-type polysilicon portions.
 11. The integrated circuit device as claimed in claim 10 further comprising, a first isolation structure, and a second isolation structure spaced apart from the first isolation structure, wherein the p-type polysilicon portion overlaps the first isolation structure and the n-type polysilicon portion overlaps the second isolation structure.
 12. The integrated circuit device as claimed in claim 11, further comprising a diffused region inside a well region adjacent one of the first isolation structure and second isolation structure, wherein the diffused region is doped with a same impurity as the well region.
 13. The integrated circuit device as claimed in claim 12, wherein the well region is biased to control the at least one substrate-biased silicon diode for providing electrostatic discharge protection.
 14. The integrated circuit device as claimed in claim 12, wherein the diffused region is biased to cause the well region to be biased to control the at least one substrate-biased silicon diode for providing electrostatic discharge protection.
 15. The integrated circuit device as claimed in claim 8, wherein the at least one substrate-biased silicon diode includes a p-portion and an n-portion, and wherein the signal pad is coupled to the p-portion of the at least one substrate-biased silicon diode.
 16. The integrated circuit device as claimed in claim 8, further comprising a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one substrate-biased silicon diode.
 17. The integrated circuit device as claimed in claim 8, wherein the signals from the signal pad are electrostatic pulses.
 18. The integrated circuit device as claimed in claim 16, wherein the detection circuit comprises a resistor-capacitor circuit having a delay constant longer than the duration of the signals from the signal pad.
 19. The integrated circuit device as claimed in claim 16, wherein the detection circuit comprises a resistor-capacitor circuit coupled in parallel to a transistor network.
 20. The integrated circuit device as claimed in claim 16, wherein the detection circuit includes a first transistor, a second transistor, and a resistor-capacitor circuit, and wherein a gate of the first transistor is coupled to a gate of the second transistor and the resistor-capacitor circuit.
 21. The integrated circuit device as claimed in claim 20, wherein a drain of the first transistor and a drain of the second transistor are coupled to a substrate of the at least one substrate-biased silicon diode to provide a bias voltage.
 22. The integrated circuit device as claimed in claim 20, wherein a source of the first transistor is coupled to a V_(DD) signal and a source of the second transistor is coupled to a Vss signal.
 23. An integrated circuit device receiving signals from a signal pad, comprising: a first plurality of serially coupled substrate-biased silicon diodes responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals, each of the first plurality of substrate-biased silicon diodes including a p-portion and an n-portion; a second plurality of serially coupled substrate-biased silicon diodes responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals, each of the second plurality of substrate-biased silicon diodes including a p-portion and an n-portion; and a detection circuit for detecting signals from the signal pad and providing a bias voltage to the first and second plurality of substrate-biased silicon diodes, wherein the signal pad is coupled to the p-portion of one of the first plurality of substrate-biased silicon diodes and the n-portion of one of the second plurality of the substrate-biased silicon diodes.
 24. The integrated circuit device as claimed in claim 23, wherein the detection circuit comprises a first transistor, a second transistor, and a resistor-capacitor network, and wherein a gate of the first transistor is coupled to a gate of the second transistor and the resistor-capacitor circuit.
 25. The integrated circuit device as claimed in claim 24, wherein a drain of the first transistor and a drain of the second transistor are coupled to a substrate of the first and second plurality of substrate-biased silicon diodes to provide a bias voltage to the first and second plurality of substrate-biased silicon diodes.
 26. An integrated circuit device, comprising a semiconductor substrate; an insulator layer disposed over the semiconductor substrate; a silicon layer disposed over the insulator layer, including a first isolation structure formed inside the silicon layer, and a second isolation structure formed inside the silicon layer and spaced apart from the first isolation structure; a dielectric layer disposed over the silicon layer; and a layer of silicon, disposed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between and contiguous with the p-type and n-type portions.
 27. The integrated circuit device as claimed in claim 26, wherein the center portion of the layer of silicon overlaps a portion of the silicon layer between the first and second isolation structures.
 28. The integrated circuit device as claimed in claim 26, wherein the portion of the silicon layer between the first and second isolation structures is biased to provide electrostatic discharge protection.
 29. A silicon-on-insulator circuit device receiving signals from a signal pad, comprising at least one base-biased silicon diode, responsive to the signals from the signal pad, for providing electrostatic discharge protection.
 30. The silicon-on-insulator circuit device as claimed in claim 29, wherein each of the at least one base-biased silicon diodes includes a p-type polysilicon portion, an n-type polysilicon portion and a center polysilicon portion disposed between and contiguous with the p-type and n-type polysilicon portions.
 31. The silicon-on-insulator circuit device as claimed in claim 29, wherein the silicon-on-insulator circuit device is biased to control the at least one base-biased silicon diode.
 32. An integrated circuit device receiving signals from a signal pad, comprising one or more serially coupled base-biased silicon diodes, responsive to the signals from the signal pad, for providing electrostatic discharge protection.
 33. The integrated circuit device as claimed in claim 32, further comprising a detection circuit for detecting signals from the signal pad and providing a bias voltage to the one or more base-biased silicon diodes, wherein the detection circuit comprises a resistor-capacitor network coupled in parallel to a transistor network.
 34. The integrated circuit device as claimed in claim 33, wherein the transistor network includes a first transistor and a second transistor, and wherein a gate of the first transistor is coupled to a gate of the second transistor and the resistor-capacitor network, and wherein a drain of the first transistor and a drain of the second transistor are coupled to a base of the one or more base-biased silicon diodes to provide a bias voltage.
 35. A method for protecting a silicon-on-insulator device from electrostatic discharge, comprising the steps of: providing a signal to the device through a silicon-on-insulator circuit; providing a base-biased silicon diode in the silicon-on-insulator circuit; and protecting the device from electrostatic discharge with the base-biased silicon diode.
 36. A method for protecting a complementary metal-oxide semiconductor device from electrostatic discharge, comprising the steps of: providing a signal to the device through a complementary metal-oxide semiconductor circuit; providing a substrate-biased silicon diode in the complementary metal-oxide semiconductor circuit; and protecting the device from electrostatic discharge produced from the signal with the substrate-biased silicon diode.
 37. A method for forming a silicon diode, comprising the steps of: forming a first silicon layer; forming a first isolation structure and a second isolation structure inside the first silicon layer, the first isolation structure being spaced apart from the second isolation structure; forming a dielectric layer over the silicon layer; forming a second silicon layer over the dielectric layer; forming dielectric spacers contiguous with the second silicon layer; implanting a first impurity having a first concentration into a first portion and a second portion of the second silicon layer, the first portion being contiguous with the second portion and the second portion overlapping a region of the first silicon layer between the first isolation structure and the second isolation structure; implanting a first impurity having a second concentration into the first portion of the second silicon layer, wherein the second concentration is greater than the first concentration; and implanting a second impurity into a third portion of the second silicon layer, wherein the third portion is contiguous with the second portion.
 38. The method as claimed in claim 37, wherein the silicon layer is a semiconductor substrate.
 39. The method as claimed in claim 37, further comprising a step of forming a well region inside the semiconductor substrate, wherein the first and second isolation structures are disposed inside the well region.
 40. The method as claimed in claim 37, wherein the first impurity is an n-type impurity and the second impurity is a p-type impurity.
 41. The method as claimed in claim 37, wherein the first impurity is a p-type impurity and the second impurity is an n-type impurity.
 42. The method as claimed in claim 37, wherein the step of forming a first and second isolation structures comprises the steps of forming a first trench and a second trench spaced apart from the first trench in the silicon layer, and providing a dielectric material in the first and second trenches.
 43. The method as claimed in claim 37, wherein the step of forming a dielectric layer includes a step of growing an oxide layer.
 44. The method as claimed in claim 37, wherein the steps of implanting a first impurity having a first concentration and implanting a first impurity having a second concentration create a diffused region adjacent one of first and second field isolation structures.
 45. The method as claimed in claim 37, wherein the step of implanting a first impurity having a first concentration includes the steps of providing a photoresist over the first silicon layer and the second silicon layer, patterning and defining the photoresist to expose the first portion and the second portion of the second silicon layer, implanting the first impurity into the first portion and the second portion, and removing the photoresist.
 46. The method as claimed in claim 37, wherein the step of implanting a second impurity includes the steps of providing a photoresist over the second silicon layer and the silicon layer, patterning and defining the photoresist to expose the third portion of the second silicon layer, implanting the second impurity into the third portion, and removing the photoresist.
 47. The method as claimed in claim 37, further comprising: defining a substrate; forming a layer of insulator over the substrate; and forming the layer of silicon over the insulator layer.
 48. A method for forming a base-biased silicon diode, comprising the steps of: forming a first and second isolation structures inside a silicon layer; defining a base region inside the silicon layer, the base region being disposed between and contiguous with the first and second isolation structures; forming a dielectric layer over the well region; forming a layer of silicon over the dielectric layer; implanting a first impurity having a first concentration into a first portion and a second portion of the silicon layer, wherein the first portion is contiguous with the second portion and the second portion overlapping a region of the silicon layer between the first isolation structure and the second isolation structure; implanting a first impurity having a second concentration into the first portion and second portion of the silicon layer, wherein the second concentration is greater than the first concentration; and implanting a second impurity into a third portion of the silicon layer, wherein the third portion is contiguous with the second portion and overlaps the second isolation structure.
 49. The method as claimed in claim 48, wherein the silicon layer is a silicon layer of a silicon-on-insulator structure.
 50. A method for forming a substrate-biased silicon diode, comprising the steps of: forming a first isolation structure and a second isolation structure spaced apart from the first isolation structure inside a silicon layer; forming a dielectric layer over the silicon layer; forming a layer of silicon having two ends over the dielectric layer; forming dielectric spacers contiguous with the two ends of the silicon layer; implanting a first impurity having a first concentration into a first portion and a second portion of the silicon layer, wherein the first portion is contiguous with the second portion and overlaps the first isolation structure; implanting a second impurity into a third portion of the silicon layer, wherein the third portion is contiguous with the second portion and overlaps the second isolation structure; and implanting a first impurity having a second concentration into the first portion of the silicon layer, wherein the second concentration is greater than the first concentration.
 51. The method as claimed in claim 50, wherein the step of implanting a second impurity creates a diffused region adjacent one of first and second field isolation structures.
 52. An integrated circuit device used for electrostatic discharge protection, comprising: a semiconductor substrate; a dielectric layer disposed over the substrate; and a layer of silicon, formed over the dielectric layer, including a p-type portion and an n-type portion.
 53. An integrated circuit device used for electrostatic discharge protection, comprising: a semiconductor substrate; a dielectric layer disposed over the substrate; a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion, and a center portion disposed between the n-type and p-type portions. 